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How to probe a signal in verilog and VHDL.

stanleyao

Hi all,

I encounter a problems.

My design hierarchy is

TOP(VHDL) - MODULE_VHD

                      |-MODULE_VERILOG

I try to probe signal of MODULE_VHD in the MODLE_VERILOG, but the signal path doesn't work.

 

I use the following description to assign SIG to PROBE_SIG.

initial $nc_mirror("PROBE_SIG",":TOP:MODULE_VHD:SIG","");

But it shows the message, ncsim: *E,PNOOBJ: Path element could not be found: TOP.

How to solve problem? Thanks.:)

Parents

  • Hi,

    Sounds like you have defined the items correctly.  Do you have a simple example?  If so please send it to me (jrodrig@cadence.com).

    As another option you can try to place the ncmirror code in the vhdl block.  To do that add the following to the vhdl:

    library ncutils;

    use ncutils.ncutilities.all;

    then include the nc_mirror line in a process block (and don't include the $ sign):

    process

    begin

      nc_mirror (":path:to:verilog:item", ":path:to:vhdl:item", "");

    end process;

    Best regards,

    Mickey

Reply

  • Hi,

    Sounds like you have defined the items correctly.  Do you have a simple example?  If so please send it to me (jrodrig@cadence.com).

    As another option you can try to place the ncmirror code in the vhdl block.  To do that add the following to the vhdl:

    library ncutils;

    use ncutils.ncutilities.all;

    then include the nc_mirror line in a process block (and don't include the $ sign):

    process

    begin

      nc_mirror (":path:to:verilog:item", ":path:to:vhdl:item", "");

    end process;

    Best regards,

    Mickey

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