How to probe a signal in verilog and VHDL.

Hi,

Sounds like you have defined the items correctly.  Do you have a simple example?  If so please send it to me (jrodrig@cadence.com).

As another option you can try to place the ncmirror code in the vhdl block.  To do that add the following to the vhdl:

library ncutils;

use ncutils.ncutilities.all;

then include the nc_mirror line in a process block (and don't include the $ sign):

process

begin

  nc_mirror (":path:to:verilog:item", ":path:to:vhdl:item", "");

end process;

Best regards,

Mickey

Hi Mickey,

 Thanks.

I wrote a simple sample as below.

entity TOP is
    ....

end entity TOP;

architecture Beh of TOP is

  component MODULE_VHDL is

  end component MODULE_VHDL;
 

  component MODULE_VERILOG is

  end component MODULE_VERILOG;

end architecture Beh

in the MODULE_VERILOG.

module MODULE_VERILOG();

  reg probe_sig;

  initial $nc_mirror("prob_sig",":TOP:MODULE_VHDL:sig","");

endmodule

but it will show the message "ncsim: *E,PNOOBJ: Path element could not be found: TOP."

I want to probe the signal in the MODULE_VHDL, but it looks like only signal below the hierarchy of MODULE_VERILOG could be probed.

Is it correct?

BR,

Stanley

Hi Stanleyao,

Don't include TOP in the VHDL path.  in VHDL the ":" indicates the top and then everything else is relative to that instance.  So the path for the vhdl item is ":<instance of MODULE_VHDL>:sig"

 For example:

test.vhd

-------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture vhdl of test is

component dff
       port (d: in std_logic;
             clk: in std_logic;
             q: out std_logic);
end component;

component nc_mirror_example
end component;

signal clk: std_logic := '0';
signal d: std_logic;
signal q: std_logic;

begin
 clk <= not clk after 20 ns;

 process
 begin
  wait for 3 ns; 
  d <= '0';
  wait for 5 ns;
  d <= '1';
  wait for 13 ns;
  d <= '0';

 end process;

 inst:dff port map (d, clk, q); 
 ncmirror_test_inst:nc_mirror_example;

end vhdl;

------------------------------------------------------------------

dff.vhd

------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity dff is
 port ( d, clk: in std_logic;
  q: out std_logic);
end dff;

architecture behave of dff is
begin
   process (clk)
   begin
      if (clk = '1' and clk'event) then
         q <= d;
      end if;
   end process;

end behave;

----------------------------------------------------

nc_mirror_example.v

--------------------------------------------------- 

module nc_mirror_example;
reg probe_sig;
initial
  $nc_mirror ("probe_sig", ":inst:q", "");

endmodule
-------------------------------------------------

Let me know if that helps.

Best regards,
Mickey

Hi Mickey,

It works!

I mistake the meaning of ":" in VHDL.

Thanks a lot!! :)

Best Regards,

Stanley