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How to probe a signal in verilog and VHDL.

stanleyao

Hi all,

I encounter a problems.

My design hierarchy is

TOP(VHDL) - MODULE_VHD

                      |-MODULE_VERILOG

I try to probe signal of MODULE_VHD in the MODLE_VERILOG, but the signal path doesn't work.

 

I use the following description to assign SIG to PROBE_SIG.

initial $nc_mirror("PROBE_SIG",":TOP:MODULE_VHD:SIG","");

But it shows the message, ncsim: *E,PNOOBJ: Path element could not be found: TOP.

How to solve problem? Thanks.:)

Parents

  • Hi Stanleyao,

    Don't include TOP in the VHDL path.  in VHDL the ":" indicates the top and then everything else is relative to that instance.  So the path for the vhdl item is ":<instance of MODULE_VHDL>:sig"

     For example:

    test.vhd

    -------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity test is
    end test;


    architecture vhdl of test is

    component dff
           port (d: in std_logic;
                 clk: in std_logic;
                 q: out std_logic);
    end component;

    component nc_mirror_example
    end component;

    signal clk: std_logic := '0';
    signal d: std_logic;
    signal q: std_logic;

    begin
     clk <= not clk after 20 ns;

     process
     begin
      wait for 3 ns; 
      d <= '0';
      wait for 5 ns;
      d <= '1';
      wait for 13 ns;
      d <= '0';

     end process;


     inst:dff port map (d, clk, q); 
     ncmirror_test_inst:nc_mirror_example;

    end vhdl;

    ------------------------------------------------------------------

    dff.vhd

    ------------------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity dff is
     port ( d, clk: in std_logic;
      q: out std_logic);
    end dff;


    architecture behave of dff is
    begin
       process (clk)
       begin
          if (clk = '1' and clk'event) then
             q <= d;
          end if;
       end process;

    end behave;

    ----------------------------------------------------

    nc_mirror_example.v

    --------------------------------------------------- 

    module nc_mirror_example;
    reg probe_sig;
    initial
      $nc_mirror ("probe_sig", ":inst:q", "");

    endmodule
    -------------------------------------------------

     

    Let me know if that helps.

    Best regards,
    Mickey

Reply

  • Hi Stanleyao,

    Don't include TOP in the VHDL path.  in VHDL the ":" indicates the top and then everything else is relative to that instance.  So the path for the vhdl item is ":<instance of MODULE_VHDL>:sig"

     For example:

    test.vhd

    -------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity test is
    end test;


    architecture vhdl of test is

    component dff
           port (d: in std_logic;
                 clk: in std_logic;
                 q: out std_logic);
    end component;

    component nc_mirror_example
    end component;

    signal clk: std_logic := '0';
    signal d: std_logic;
    signal q: std_logic;

    begin
     clk <= not clk after 20 ns;

     process
     begin
      wait for 3 ns; 
      d <= '0';
      wait for 5 ns;
      d <= '1';
      wait for 13 ns;
      d <= '0';

     end process;


     inst:dff port map (d, clk, q); 
     ncmirror_test_inst:nc_mirror_example;

    end vhdl;

    ------------------------------------------------------------------

    dff.vhd

    ------------------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity dff is
     port ( d, clk: in std_logic;
      q: out std_logic);
    end dff;


    architecture behave of dff is
    begin
       process (clk)
       begin
          if (clk = '1' and clk'event) then
             q <= d;
          end if;
       end process;

    end behave;

    ----------------------------------------------------

    nc_mirror_example.v

    --------------------------------------------------- 

    module nc_mirror_example;
    reg probe_sig;
    initial
      $nc_mirror ("probe_sig", ":inst:q", "");

    endmodule
    -------------------------------------------------

     

    Let me know if that helps.

    Best regards,
    Mickey

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