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Unresolved adapter error: ERR_DID_NOT_FIND_ADAPTER

random

Hi all

I have a mixed environment with a vhdl testbench and i am trying to access an internal signal which is verilog. I had a working environment when i used older version of specman 5.xx a couple of years ago. When i try the same with the new version of specman 8.1x, I get the following error.

I constrained the agent() of the unit instance to verilog.

keep soft abc.._u.agent() == "verilog";

    Opening file for message: abc_testbench.elog
   *** Error: ERR_DID_NOT_FIND_ADAPTER: Unresolved adapter identification name 'Verilog'.
When you set this condition to a severity of WARNING or IGNORE, then
the NULL_SIM adapter is used instead.

 

Any help in resolving this is greatly appreciated.

Parents

  •  I figured the problem is because i did not recreate the stubs file. It will take a while before i can create a stubs file for the entire project as i have to wait for others to clean up their code.. but hopefully it will work.. if not, i will repost the query.

    Thanks

    kk

Reply

  •  I figured the problem is because i did not recreate the stubs file. It will take a while before i can create a stubs file for the entire project as i have to wait for others to clean up their code.. but hopefully it will work.. if not, i will repost the query.

    Thanks

    kk

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