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IUS82s012: is this legal "for ( genvar g = 0; g < 4; ++g ) ..."?

cubicle82

I tried auto-declaring a generate-var inside a generate-block:

module a;

wire [3:0] x;

generate
for ( genvar g = 0; g < 4; ++g ) begin :gen_g
    assign x[g] = 1'b0;
end : gen_g
endgenerate

endmodule : a

irun-8.2s012 gives me this error-message:

for ( genvar g = 0; g < 4; ++g ) begin :gen_g
           |
ncvlog: *E,FNDKWD (a.sv,6|11): A Verilog keyword was found where an identifier was expected.

 

Naturally, I can just move the 'genvar g'  oustide of the for() block.  But it would be nice to be able to use inline-style of loop-var declaration with genvars.

Parents

  • RE: ++g vs g++

    Oh, it's an old habit! In C/C++ code, I very rarely embed a dec/inc index-operation with data-manipulation.  I.e.:

      str[ i++ ] = 0;

      or my least favorite: *optr++ = *iptr++;

    Instead, I tend to separate it into multiple statements, simply because I find it easier to read.  Other programmers will use both forms, depending on the loop-situation.  Although the code is more compact, I (personally) find it harder to read, especially late at night after staring at the monitor for 5 hours :)

Reply

  • RE: ++g vs g++

    Oh, it's an old habit! In C/C++ code, I very rarely embed a dec/inc index-operation with data-manipulation.  I.e.:

      str[ i++ ] = 0;

      or my least favorite: *optr++ = *iptr++;

    Instead, I tend to separate it into multiple statements, simply because I find it easier to read.  Other programmers will use both forms, depending on the loop-situation.  Although the code is more compact, I (personally) find it harder to read, especially late at night after staring at the monitor for 5 hours :)

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