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Verilog Monitor to Check 'X' state of a Clock from the DUT.

RaghavNS

Hi,

I want to find out the clock driven from the DUT doesn't have a 'X' State. I tried different ways of finding the 'X' State in the clock but every effort was without success.
always @ clock
if ( clock === 1'bX)
Flag Error
always @ clock
if (clock !== 1'b0 | clock !== 1'b1)
Flag error
while (clock === 1'bX)
Flag error
None of the above code Flagged an Error
Can anyone please provide me a solution for finding the 'X' state in a Signal/Clock?

I require the monitor in Verilog.

Thanks
Raghav

Parents
  • Mickey

    Hi Raghav,

    There is an assertion check in the IAL library that you can use to do this.  to use it do the following:

    1)  add an instance of ial_never_unknown_async to your verilog code.  It can either be in your current testbench or within a new standalone module that has OOMR references to the appropriate signals and connect reset_n, test_expr, and enable pins as applicable

    2)  add the following to your compile line to compile the assertion library, include the appropriate components, and invoke the assertion:  <IUS_install>/tools/ial/verilog/*.vlib  -<IUS_install>/tools/ial/include -assert

     an example would be as follows:

    module clock;
    reg clk;

    initial
      begin
      clk <= 1'b0;
      forever #5 clk <= !clk;
      end
     
    initial
      begin
       #7 clk <= 1'bx;
       #10 $finish;
      end
     
    ial_never_unknown_async test (.reset_n(1'b1), .test_expr(clk), .enable(1'b1));

    endmodule

    Hope that helps.

    Mickey

Reply
  • Mickey

    Hi Raghav,

    There is an assertion check in the IAL library that you can use to do this.  to use it do the following:

    1)  add an instance of ial_never_unknown_async to your verilog code.  It can either be in your current testbench or within a new standalone module that has OOMR references to the appropriate signals and connect reset_n, test_expr, and enable pins as applicable

    2)  add the following to your compile line to compile the assertion library, include the appropriate components, and invoke the assertion:  <IUS_install>/tools/ial/verilog/*.vlib  -<IUS_install>/tools/ial/include -assert

     an example would be as follows:

    module clock;
    reg clk;

    initial
      begin
      clk <= 1'b0;
      forever #5 clk <= !clk;
      end
     
    initial
      begin
       #7 clk <= 1'bx;
       #10 $finish;
      end
     
    ial_never_unknown_async test (.reset_n(1'b1), .test_expr(clk), .enable(1'b1));

    endmodule

    Hope that helps.

    Mickey

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