to find out the clock driven from the DUT doesn't have a 'X' State. I
tried different ways of finding the 'X' State in the clock but every
effort was without success.always @ clockif ( clock === 1'bX)Flag Erroralways @ clockif (clock !== 1'b0 | clock !== 1'b1)Flag errorwhile (clock === 1'bX)Flag errorNone of the above code Flagged an ErrorCan anyone please provide me a solution for finding the 'X' state in a Signal/Clock?
I require the monitor in Verilog.
There is an assertion check in the IAL library that you can use to do this. to use it do the following:
1) add an instance of ial_never_unknown_async to your verilog code. It can either be in your current testbench or within a new standalone module that has OOMR references to the appropriate signals and connect reset_n, test_expr, and enable pins as applicable
2) add the following to your compile line to compile the assertion library, include the appropriate components, and invoke the assertion: <IUS_install>/tools/ial/verilog/*.vlib -<IUS_install>/tools/ial/include -assert
an example would be as follows:
module clock;reg clk;
initial begin clk <= 1'b0; forever #5 clk <= !clk; end initial begin #7 clk <= 1'bx; #10 $finish; end ial_never_unknown_async test (.reset_n(1'b1), .test_expr(clk), .enable(1'b1));
Hope that helps.
woops. minor correction on the command line... <IUS_install>/tools/ial/verilog/*.vlib -incdir <IUS_install>/tools/ial/include -assert