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Verilog Monitor to Check 'X' state of a Clock from the DUT.

RaghavNS

Hi,

I want to find out the clock driven from the DUT doesn't have a 'X' State. I tried different ways of finding the 'X' State in the clock but every effort was without success.
always @ clock
if ( clock === 1'bX)
Flag Error
always @ clock
if (clock !== 1'b0 | clock !== 1'b1)
Flag error
while (clock === 1'bX)
Flag error
None of the above code Flagged an Error
Can anyone please provide me a solution for finding the 'X' state in a Signal/Clock?

I require the monitor in Verilog.

Thanks
Raghav

Parents
  • Mickey

    woops.  minor correction on the command line...  <IUS_install>/tools/ial/verilog/*.vlib  -incdir <IUS_install>/tools/ial/include -assert

Reply
  • Mickey

    woops.  minor correction on the command line...  <IUS_install>/tools/ial/verilog/*.vlib  -incdir <IUS_install>/tools/ial/include -assert

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