Verilog, System Verilog and SystemC

 Hi Jasonkee111,

Good questions.  As you have discovered there are many languages available for design and verification with various advantages/disadvantages.  I will try to give you some recommendations based on my experience working with many customers.

For RTL design, Verilog is still the main language being used today (alongside VHDL).  SystemVerilog offers some nice new capabilities to Verilog RTL and these new design constructs are incremental and fairly easy for a Verilog RTL designer to understand.  These features are mainly "convenience" syntax enhancements but do very little to raise the level of abstraction beyond the register transfer level.  If you are doing directed testing, you can use Verilog to write a basic testbench and directed tests for your design.  However, for verification most people are moving to a more automated approach to verification applying Coverage Driven and Metric Driven methodology, where you define your verification goals using functional coverage, leverage constrained-random stimulus generation to create the tests automatically, and define your checks independent of your tests.  The two best languages being used today for this type of advanced verification are e and SystemVerilog, where a lot of users find the e language to be easier and more efficient for building this type of testbench.  SystemVerilog can also be a good choice here, but you should keep in mind that this is a completely separate part of the language from the SystemVerilog constructs you use for design.  SystemC provides a class library which extends C++ and defines a common way to write Transaction Level Models (TLM) which are at a much higher abstraction level compared to Verilog/SystemVerilog RTL models.  SystemC has traditionally been used for creating models architectural exploration and for providing an early model of the hardware design for software development.  Cadence is now offering a synthesis tool, C-to-Silicon, which can be used to synthesize the SystemC TLM.  This enables capturing the design at a much higher level of abstraction, while still being able to use the same model for architectural analysis and software development.  As part of this offering, Cadence is building a complete methodology for enabling both design and verification to start at the TLM level.  For the verification at the TLM level, we are leveraging the same automated Metric driven approach that people are applying on RTL designs today, where e is a more natural choice for the verification language since SystemVerilog was built primarily for Verilog/RTL verification.  If you decide to use e or SystemVerilog for verification, you should probably leverage the Open Verification Methodology (OVM) which provides class libraries, utilities, and methodology guidelines for making it easier to write SystemVerilog or e testbenches. 

Hopefully that clears up some of your questions.

Regards,
Mike

Hi Mike.

 What do  you mean by testing using Verilog? What differentiate the test and verify?

System Verilog for RTL design is mucher higher on abstraction compared to Verilog. 

if i use System Verilog for RTL design, what is the disadvantage?  

What is the thing Verilog can do while System Verilog cant?

What do  you mean by testing using Verilog? What differentiate the test and verify?

In Verilog, you can write procedural code to define tests to stimulate and check your design.  This is a manual process since you have to think of each test, and then write the stimulus and check the expected behavior.  This is a way to "verify" the design, but it is a "test-driven" manual approach, and not very efficient or effective.  

 if i use System Verilog for RTL design, what is the disadvantage? 

You need to make sure that all the tools you use support the SystemVerilog constructs you intend to use.  This is the only disadvantage.

What is the thing Verilog can do while System Verilog cant? 

SystemVerilog is a superset of Verilog.