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Verilog, System Verilog and SystemC

jasonkee111

 

i confused about these languages.

Can somebody clarify on it:
1. For RTL design, Verilog or System Verilog should be used?Most of the article about System Verilog focus on verification. Which language is easier to user and perform well?is there anything that verilog can do and system verilog cant? since a lot of hardware design engineer still use verilog for RTL design.


2. If the RTL design is written in Verilog, is it possible to use System Verilog to verify it?

3. Is it possible to mix Verilog, System Verilog and System C in one design? e.g Model in System C, the design written in verilog, System Verilog for verification

4. Since System C and System Verilog both also system level design, when to use System C and System Verilog?According to my understanding, System C is used in starting of system design in order to predict the performance of software and hardware while System Verilog is used in verification for RTL.

5. How to determine which portion in a system should go to softcore or hardcore?

6. I read a lot of threads that mention to use system verilog instead of system c for system level design(hardware design), is it correct? if in the case of SoC, where it involve the software and hardware, is system verilog have this kind of ability to synthesis(not sure the term to use) it?


Thanks and sorry if asking silly question(s)..

Parents

  • What do  you mean by testing using Verilog? What differentiate the test and verify?

    In Verilog, you can write procedural code to define tests to stimulate and check your design.  This is a manual process since you have to think of each test, and then write the stimulus and check the expected behavior.  This is a way to "verify" the design, but it is a "test-driven" manual approach, and not very efficient or effective.  

     if i use System Verilog for RTL design, what is the disadvantage? 

    You need to make sure that all the tools you use support the SystemVerilog constructs you intend to use.  This is the only disadvantage.

    What is the thing Verilog can do while System Verilog cant? 

    SystemVerilog is a superset of Verilog.

Reply

  • What do  you mean by testing using Verilog? What differentiate the test and verify?

    In Verilog, you can write procedural code to define tests to stimulate and check your design.  This is a manual process since you have to think of each test, and then write the stimulus and check the expected behavior.  This is a way to "verify" the design, but it is a "test-driven" manual approach, and not very efficient or effective.  

     if i use System Verilog for RTL design, what is the disadvantage? 

    You need to make sure that all the tools you use support the SystemVerilog constructs you intend to use.  This is the only disadvantage.

    What is the thing Verilog can do while System Verilog cant? 

    SystemVerilog is a superset of Verilog.

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