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  3. Problem with follow simple code

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Problem with follow simple code

navis
navis over 15 years ago

 Hello all,

I'm trying to use some simple class wirh SystemVerilog.

But NCSim dosn't work properly. What is the reason?

Here is the code which is very basic and veri simple:

 

module class_opt(output logic x);

class gen;
    task display_d(bit [3:0] in);
        $display ("You entered %d",  in);
    endtask   
    task sig_gen;
        #100;
        x = 1'b1;
        #100;
        x = 1'b0;
    endtask
endclass:gen

gen a = new();

initial begin

    in = 1;
    a.display_d(in);
    in = 2;
    a.display_d(in);
    in = 3;
    a.display_d(in);
    a.sig_gen;
    a.sig_gen;
    a.sig_gen;
    a.sig_gen;
   
end
endmodule

 Any sugestions are welcome.

Thanks and regards

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  • TAM1
    TAM1 over 15 years ago

    The code as given doesn't declare the local variable "in" which is assigned to 1, 2 and 3 in the initial block. When I add a declaration for it, everything seems to run fine. Note that this "in" is separate from the class method's parameter which happens to share the name "in", but in a different scope.

     

    module class_opt(output logic x);
      bit [3:0] in;   // this is the module's "in" variable
      class gen;
      task display_d(bit [3:0] in);  // this is the task's input parameter

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  • navis
    navis over 15 years ago

     Thank you for the answer, but the real problem is that I'm not able to drive output "x".

     

    Best regards

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  • Mickey
    Mickey over 15 years ago
    Hi Navis, Are you including systemverilog parsing? if you are using "ncverilog" or "ncvlog" you need to add -sv to your command line. if you are using "irun" does the file being compiled have a .sv extension? Best regards, Mickey
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  • navis
    navis over 15 years ago

     Hi Mickey,

    Thank you answering. Yes I do that.

    Bellow is my command line

    ncvlog -work worklib -cdslib /home/Projects/SysVerilog/cds.lib -logfile ncvlog.log -errormax 15 -update -linedebug -status -sv /home/Projects/SysVerilog/hdl/Class_opit/Calss_opt.sv

     

    What is strange, I tried this code with some other simulator, and it was able to drive this output.

     

    Bst regards,

     

     

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  • TAM1
    TAM1 over 15 years ago

    After I had added the declaration "reg [3:0] in;" to the module's source code, I did try running the simulation and everything appeared fine to me. What is it you are expecting that you don't see?

    In my sim, the output "x" is 1'bx for 100 ns until the first assignment in a.sig_gen occurs and it toggles between 1 and 0 after that.

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  • navis
    navis over 15 years ago

     Thank you for the answer.

    So it seems that I do something wrong, but I cna't understand what is it.

    In My simulation the output "X" stays in x forever.

    I've made some trial, declaring local variable into the class, and I was able to see that this internal variable is togling.

    After I removed it, and output x just do nothing.

    Could it be to the NCsim  version? I'm using NCLaunch 08.20-s008

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  • TAM1
    TAM1 over 15 years ago

    I'm afraid that I don't have anything more to add. As I said, it's a very simple example that works fine for me, even in nclaunch. Is there another ncsim and SystemVerilog user in your company who can look over your shoulder and see if there might be something very simple in your setup that you are missing?

    Try adding some $display statements in the code like you did for the display_d method. Something like:
      x = 1'b1;
      $display("Setting x to: ",x);

    Then try running from the command line to make everything as simple as can be:

        irun -sv yourfilename.v

    or, if you want the GUI:

        irun -sv -access rwc -gui yourfilename.v

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  • navis
    navis over 15 years ago

     Hi,

    thank you again for the answer. 

    Actualy it was woked as you said. But the problem was that I wasn't able to se the signal change on the waveform.

    So I added display function, and it shows me that the signal is changing. After I added some extra modules and I get the output and connected it to the other module. after that I was able to see that the signal is changing in wave form as well.

     

    Regards,

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