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Clocking blocks /cycle based sampling and driving

hipooja

Hi,

I read that clocking block / cycle based simulation in SV promotes reusability.Why is that so? I understand that interface definition simplifies the signal connection  How does this promote reusability?

Regards,

Pooja Vaishnav.

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  • Vinayhonnavara

     Hello Pooja,

     Assume that you are working on developing new features for an existing project. If you have a central location where you have bundled up the wires and signals, you can simply add more signals without adding new port connections for each of the module accessing it. Also you will be driving just interface signals or sampling them. This promotes re-usabililty as you are just concerned with adding signals in the interface and in driving or sampling in your respective blocks.

    For your second part of the question "clocking blocks seperate signal functionality",  clocking blocks are mainly used by testbenches. If your testbench was in verilog then you would be working in the same timing region and there would be some inherent race conditions. However since clocking blocks are mainly used in testbench in SV which is in a different timing region, you would minimize the race conditions. Thus you need to seperate Signal functionality (active, observed and postpone ) from the reactive region in testbench. This is the essence of seperating timing regions for signal functionality

     

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  • Vinayhonnavara

     Hello Pooja,

     Assume that you are working on developing new features for an existing project. If you have a central location where you have bundled up the wires and signals, you can simply add more signals without adding new port connections for each of the module accessing it. Also you will be driving just interface signals or sampling them. This promotes re-usabililty as you are just concerned with adding signals in the interface and in driving or sampling in your respective blocks.

    For your second part of the question "clocking blocks seperate signal functionality",  clocking blocks are mainly used by testbenches. If your testbench was in verilog then you would be working in the same timing region and there would be some inherent race conditions. However since clocking blocks are mainly used in testbench in SV which is in a different timing region, you would minimize the race conditions. Thus you need to seperate Signal functionality (active, observed and postpone ) from the reactive region in testbench. This is the essence of seperating timing regions for signal functionality

     

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