Clocking blocks /cycle based sampling and driving

I also read that clocking blocks seperate signal functionality and timing and help avoid user induced races.The latter point i understand is because clocking blocks samples the signal x time before the sampling event and holds the signal y time after the sampling event ,which avoids metastability and hence X's,the former point is however unclear.

Regards,

Pooja Vaishnav

 Hello Pooja,

 Assume that you are working on developing new features for an existing project. If you have a central location where you have bundled up the wires and signals, you can simply add more signals without adding new port connections for each of the module accessing it. Also you will be driving just interface signals or sampling them. This promotes re-usabililty as you are just concerned with adding signals in the interface and in driving or sampling in your respective blocks.

For your second part of the question "clocking blocks seperate signal functionality",  clocking blocks are mainly used by testbenches. If your testbench was in verilog then you would be working in the same timing region and there would be some inherent race conditions. However since clocking blocks are mainly used in testbench in SV which is in a different timing region, you would minimize the race conditions. Thus you need to seperate Signal functionality (active, observed and postpone ) from the reactive region in testbench. This is the essence of seperating timing regions for signal functionality

I figured out that modports are the first step to reusability ,suppose there is a master and slave wherein only the direction of signal is different,then all you need to do is bunch the signals and define directions in modport and pass the modport to the constructor of the master and slave module,hence it spares the effort of defining the signals again in each module ,their direction and connections.This promotes reusability because as you said ,if signals change all you need to do is edit the interface,the same testbench code can be used incase only the signals have changed.If I2C interface is used connecting host to TX chip and the RX chip ,all you need is to define a single I2C interface and plug it to the TX,RX and host.

Secondly i learnt that clocking blocks seperate signal timing as the interface where they are defined ,contain the typical sample-hold time of the signal,thus the coder does not need to worry about this /clocking event ,all he /she needs to do is focus on the functionality.

Regards,

Pooja

 Rightly put :)