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New to SV: Disabling of assertions from a task?

I am in the process of creating SV checkers for an existing environment. I am trying to find a way to disable all assertions for a given test. The test in question is a force/check style which throws off all of the assertions. I have seen a method of doing this from TCL, but would like to do it from a task (current test method).

Any recomendations appreciated

Thanks,

Ross

TAM1 over 15 years ago

You can use the SystemVerilog $asserton, $assertoff and $assertkill system tasks to control assertion operation.
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rossbthompson over 15 years ago

Thank you, That is exactly what I needed. I was lost in my 7 open pdf files and missed that.
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StephenH over 15 years ago

rossbthompson said:
I was lost in my 7 open pdf files and missed that.

Hmm... is that a subtle dig?
Have you tried using the doc browser "cdnshelp" instead of the PDFs? The searching should generally be a lot better, and you can search across all / some of the manuals / products rather than one-at-a-time.
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rossbthompson over 15 years ago

No dig intended. Just a statement of my experience level in SV. I wasnt sure what I was looking for.
I tend to use my pc for my document reading. For Specman, I used to copy over the whole html tree and could use the search through the main web page. Is there a similar option for the other Cadence products?
current open pdf's:
ncvlog.pdf
sv_lrm.pdf
vmm_sv.pdf
iccug.pdf
sysverilog.pdf
abvwrite.pdf
abvguide.pdf
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