SV:Where to use Continuous Assign?

 An excellent documentation on continous assignments, blocking and non-blocking usage is in this document.

http://csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf

In terms of SV usage (from a testbench perspective) for all of them,  first of all SV makes a clear differentiation between verilog by not having always blocks. Second of all drives are always non-blocking to signals in the DUT. If you want to assign always to some value use initial forever. 

 On using continous assignments to be subsituted by non-blocking statements, it depends what you want to model sequential or combinational , if you want to model sequential use non-blocking statements if you want to model combinational use blocking or continous assignments.

If you are modeling a bi-directional bus you  should always use continous assignments

I'm not sure what you mean by "SV makes a clear differentiation between verilog by not having always blocks." SV is an extension of Verilog, so it certainly does have always blocks. SystemVerilog has relaxed some of the rules regarding the kinds of signals that can be updated by a continuous assignment. But that's a kind of complicated topic for a new user to get involved with.

A continuous assignment is used to place a value on a "net" datatype. A "net" datatype is a "wire", "wor" and etc. A continuous assignment is always active (that's why it is called a continuous assignment) and it immediately schedules a new value on its target when one or more of its inputs changes.

A blocking or non-blocking assignment is used to put a value on a "variable" datatype. A "variable" datatype is a "reg", "var", "integer" and etc. A blocking or nonblocking assignment is not always active. You control when it executes with the RTL code that you write. You can control both when the assignment statement executes, and when it will schedule the new value to appear on the target variable. Blocking assignments made with "=" update their target immediately. Non-blocking assignments made with "<=" wait until the end of the current timestep to update their target variables.

The reality is a little more complex than that. But I believe what I've written is a useful model to use when first learning about assignments.

Thanks TAM. This is definitely going to help. Shall post further queries regarding the same in future, if any.

Insiya