• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. SV:Where to use Continuous Assign?

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 66
  • Views 1707
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SV:Where to use Continuous Assign?

Leo1008
Leo1008 over 15 years ago

 Hi,

I am not sure of the exact usage of continuous assignments. I want to know where should one use these and what is the difference between the three types of assingments viz. Continuous, blocking and non-blocking.

Also can continuous assignments be substituted by non-blocking assingments or vice versa??

 

Thanks

Insiya

  • Cancel
Parents
  • Vinayhonnavara
    Vinayhonnavara over 15 years ago

     An excellent documentation on continous assignments, blocking and non-blocking usage is in this document.

    http://csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf

    In terms of SV usage (from a testbench perspective) for all of them,  first of all SV makes a clear differentiation between verilog by not having always blocks. Second of all drives are always non-blocking to signals in the DUT. If you want to assign always to some value use initial forever. 

     On using continous assignments to be subsituted by non-blocking statements, it depends what you want to model sequential or combinational , if you want to model sequential use non-blocking statements if you want to model combinational use blocking or continous assignments.

    If you are modeling a bi-directional bus you  should always use continous assignments

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Vinayhonnavara
    Vinayhonnavara over 15 years ago

     An excellent documentation on continous assignments, blocking and non-blocking usage is in this document.

    http://csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf

    In terms of SV usage (from a testbench perspective) for all of them,  first of all SV makes a clear differentiation between verilog by not having always blocks. Second of all drives are always non-blocking to signals in the DUT. If you want to assign always to some value use initial forever. 

     On using continous assignments to be subsituted by non-blocking statements, it depends what you want to model sequential or combinational , if you want to model sequential use non-blocking statements if you want to model combinational use blocking or continous assignments.

    If you are modeling a bi-directional bus you  should always use continous assignments

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information