Stats

  • Locked Locked
  • Replies 4
  • Subscribers 65
  • Views 14308
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

System Verilog Compilation

Sarvesh

Hi,

I am doing a simple TB using System Verilog. (My first attempt). The various classes have been defined , they are put in an environment file which instantiates all the different classes. This file is then called in a program file which is like the "Top" file for all the System Verilog logic . This is then taken to the TB_TOP file which has the RTL instance and the program block instance and the connection logic.

My  problem is this. All files including interfaces , classes compile well. When I try to use syntax "automatic" for the program declaration, I get a syntax error as it says Cadence does not support this syntax.As per definition "automatic" should make the program declaration global to be seen by all modules.(Cadence version I am using is NcVerilog 8.20).

If I do not use program then I get an elab error which says that there is no logical connection between the interfaces defined i.e. the System Verilog Top and the TB_TOP are not connected well.

Any suggestions or tips would be helpful.

Thanks in advance.

 

  • Sarvesh said:
    As per definition "automatic" should make the program declaration global to be seen by all modules.

     Why do you think 'automatic' does this? 'automatic' makes declarations of tasks and functions and of variables declared inside procedural blocks automatic by default.

    Shalom

  • Thanks. I will double check the definition in the LRM. 

    But then if I do use automatic with my "program" block declaration give an error saying that it is not supported by Cadence. Is it that Cadence does not support all the syntax in the LRM ? I mean with me using Version 8.2 I think it is fairly latest to have this support. Please let me know if you have any information.

    Regards,

  • Correct. Cadence does not yet support all of the SV syntax. I have been told that Cadence intends to make a big effort on this in 2010.

    Shalom

  • Thanks for that input. I will change my tool at least temporarily as Cadence seems to be lagging behind on this regard and for a beginner like me I will not know whether it is my fault or the tool does not support this syntax.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.