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System Verilog Compilation

Sarvesh

Hi,

I am doing a simple TB using System Verilog. (My first attempt). The various classes have been defined , they are put in an environment file which instantiates all the different classes. This file is then called in a program file which is like the "Top" file for all the System Verilog logic . This is then taken to the TB_TOP file which has the RTL instance and the program block instance and the connection logic.

My  problem is this. All files including interfaces , classes compile well. When I try to use syntax "automatic" for the program declaration, I get a syntax error as it says Cadence does not support this syntax.As per definition "automatic" should make the program declaration global to be seen by all modules.(Cadence version I am using is NcVerilog 8.20).

If I do not use program then I get an elab error which says that there is no logical connection between the interfaces defined i.e. the System Verilog Top and the TB_TOP are not connected well.

Any suggestions or tips would be helpful.

Thanks in advance.

 

Parents

  • Sarvesh said:
    As per definition "automatic" should make the program declaration global to be seen by all modules.

     Why do you think 'automatic' does this? 'automatic' makes declarations of tasks and functions and of variables declared inside procedural blocks automatic by default.

    Shalom

Reply

  • Sarvesh said:
    As per definition "automatic" should make the program declaration global to be seen by all modules.

     Why do you think 'automatic' does this? 'automatic' makes declarations of tasks and functions and of variables declared inside procedural blocks automatic by default.

    Shalom

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