System Verilog with Spice *F,INTERR - cu_check_port_var_aca

Hi,

I am trying to use a system verilog testbench to verify a spice block. The aim is to have system verilog stimulus and monitoring using real values.I have example with the stimulus side working but not the monitoring.

When I run my simple example I receive the following error during elaboration. What am I missing from the configuration to get this working?

(This testcase started off as the spice_in_middle example from the AMSD workshop)

Graeme Nunn

 ncelab: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncelab  08.20-s009
  HOSTNAME:
  OPERATING SYSTEM: Linux 2.6.9-89.0.20.ELsmp #1 SMP Mon Jan 18 12:19:33 EST 2010 x86_64
  MESSAGE: cu_check_port_var_aca - not net, class 520, file: top.sv, line:6

 Input Files:

------------------------ 
Run
------------------------ 
#! /bin/csh -f

irun    *.sv \
        *.vams \
        amscf.scs \
        -timescale 1ns/100ps \
        -mess

----------------------
pot.sp
----------------------
.subckt pot rtop rmid
r1 rtop rmid 10k
r2 rmid 0 10k
.ends

----------------------
top.sv
----------------------
module top ;

  timeunit      1ns ;
  timeprecision 1ns ;

  harness h1 (.resp(out),.sig(sig));
  pot p1 (.rtop(sig),.rmid(out));

endmodule : top
----------------------
harness.sv
----------------------
module harness (resp,sig);
        output real  sig ;
        input var real resp ;

        var real sig_r;
        assign sig=sig_r;

        initial begin
                sig_r=0.0;
                #10 sig_r=1.0;
                #10 sig_r=2.0;
                #10 sig_r=3.0;
                #10 sig_r=2.0;
                #10 sig_r=1.0;
                $finish;
        end

        always @(resp) $display("Resp has changed to %0f",resp);

endmodule

----------------------
amscf.scs
----------------------
include "./pot.sp"

* AMS Control file
include "top.scs"
amsd {
        portmap subckt=pot file="pot.pb"
        config cell=pot use=spice
        ie vsup=1.8
}

----------------------
top.scs
----------------------
simulator lang=spectre
rawFmtOpt options rawfmt=sst2fbin   maxwarnstologfile=1000 maxnotestologfile=1000
saveNodes options save=all
timeDom tran stop= 30us
----------------------
pot.pb
----------------------
 //*** pot.pb ***
//* Portbind file for:
//* SPICE subckt pot : HDL module pot
//* SPICE port  :       HDL port        :       HDL Parameters

rtop    :       rtop    :       dir=inout
rmid    :       rmid    :       dir=inout