I have a testbench where I am trying to simulate two separate designs that share some module names within their designs. For example, one is a bus controller and the other is bus master and each has a module named InterfaceIo. When I try to simulate there is a conflict of multiple modules with the same name. I have tried compiling and elaborating them separately and then referencing the libraries but I still get the error. Is there a way to black-box a module or to get around the conflict I am experiencing? Note that this is an overly simple example of the conflict in names so please don't respond with "just change the names!" This doesn't seem like it should be so difficult but I am not figuring out how to get things going. Any help will be greatly appreciated!
I assume that you're talking about Verilog rather than VHDL here!
It sounds like you are looking for the functionality provided by the "libmap" which is Verilog's equivalent to VHDL configurations.
You provide a libmap file to the compiler (ncvlog/ncelab or irun) which tells it which *.v files go into which compiled libraries, and also which instances use which modules/libraries.
I've not used it much myself, but it's well enough documented that you should be able to find your way.Fire up cdnshelp, and search for \-libmap (note: the back-slash is needed in front of the dash).