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Testbench with non-unique module names in sub-blocks

mattyc

I have a testbench where I am trying to simulate two separate designs that share some module names within their designs.  For example, one is a bus controller and the other is bus master and each has a module named InterfaceIo.  When I try to simulate there is a conflict of multiple modules with the same name.  I have tried compiling and elaborating them separately and then referencing the libraries but I still get the error.  Is there a way to black-box a module or to get around the conflict I am experiencing?  Note that this is an overly simple example of the conflict in names so please don't respond with "just change the names!"  This doesn't seem like it should be so difficult but I am not figuring out how to get things going.  Any help will be greatly appreciated!

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  • muffi
    If you are using irun, adding -allowredefinition allows irun to compile and take the second module encountered.
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  • muffi
    If you are using irun, adding -allowredefinition allows irun to compile and take the second module encountered.
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