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mixed language simulation

josephbell

Hello all

 i am doing verification of a blocks that has vhdl modules instantiated in the verilog top module. the vhdl modules are using the xilinx libraries like unisims / corelib. i have compiled the libraries and vhdl modules are picking up those libraries. i am having problem while elaborating the design. i am using following commands for simulating the design: ncvhdl -v93 -f filelist_vhdl 

ncvlog -f filelist_ver 

ncelab -access +rw +mixedlang tb_module -v93 

while elaborating i am getting following error:  ncelab: *E,CFIGTC saying the VHDL generic bit_vector type is not compatible with verilog. and the bit_vector is declared in the xilinx library primitives. 

i cannot change the type bit_vector to std_logic_vector  as these are standard libraries and ihave no permission to modify them.

can anybody help me out. 

thanks

vishal 

 

  • Hi Vishal.

    I believe that Xilinx supply both VHDL and Verilog versions of their unisim libraries. I worked with someone else this week who saw the same issue as you. In the end it turned out to be that he was using a Verilog design, with the VHDL unisim library.Afterhe switched his cds.lib to point to unisim_ver instead of unisim, it worked OK.

    Since you say your design is VHDL, perhaps you could check your cds.lib to see if you have unisim_ver in there already; if so, swap it to unisim.

    Regards.
    Steve.

  • Thanks Steve. i have already done this, instead of using VHDL unisims i changed the cds.lib to pick up the Verilog unisims. this has worked for me. Thanks for the information.

    Thanks
    Vishal

  •  

    StephenH said:

    Hi Vishal.

    I believe that Xilinx supply both VHDL and Verilog versions of their unisim libraries. I worked with someone else this week who saw the same issue as you. In the end it turned out to be that he was using a Verilog design, with the VHDL unisim library.Afterhe switched his cds.lib to point to unisim_ver instead of unisim, it worked OK.

    Since you say your design is VHDL, perhaps you could check your cds.lib to see if you have unisim_ver in there already; if so, swap it to unisim.

    Regards.
    Steve.

    me too :D

     

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  • We worked with somebody else now who noticed the exact same issue while you. Within the end it turned out to be he had been utilizing a Verilog style, using the VHDL unisim library.Afterhe changed his cds.lib in order to indicate unisim_ver rather than unisim, it proved helpful Ok.

    Because you state your style is VHDL, possibly you could check your compact disks.lib to determine for those who have unisim_ver within currently; if so, swap it to unisim.

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