mixed language simulation

Hello all

 i am doing verification of a blocks that has vhdl modules instantiated in the verilog top module. the vhdl modules are using the xilinx libraries like unisims / corelib. i have compiled the libraries and vhdl modules are picking up those libraries. i am having problem while elaborating the design. i am using following commands for simulating the design: ncvhdl -v93 -f filelist_vhdl 

ncvlog -f filelist_ver 

ncelab -access +rw +mixedlang tb_module -v93 

while elaborating i am getting following error:  ncelab: *E,CFIGTC saying the VHDL generic bit_vector type is not compatible with verilog. and the bit_vector is declared in the xilinx library primitives. 

i cannot change the type bit_vector to std_logic_vector  as these are standard libraries and ihave no permission to modify them.

can anybody help me out. 

thanks

vishal