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What is the correct syntax for forcing signal in a Verilog testbench

Blaise70

Hi All,

I have a Verilog testbench where I would like to force some signals.

I'm using the following code in my Verilog file:

$nc_force("/full_path/sugnal_name","'b1");

Compilation seems to be OK, but during run-time I get the following error message:

ncsim: *E,SETNEL: Poorly formed string/enumeration literal: 'b1.

Can someone give me the correct syntax for the value to be forced? I have already tryed a lot of different strings, but none of them works.

Thanks in advance.

Best regards,

Blaise70

Parents

  • Did you try without the 'b part?

    In case you're not aware, the 6 letter error code can be used to display additional information:

    % nchelp ncsim SETNEL

    nchelp: 09.20-s031: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    ncsim/SETNEL =
            An attempt was made to force/nc_mirror a VHDL object using an invalid
            string or enumeration literal.
            Examples:
                    {"0001"}        -- legal
                    {"howdy"}       -- legal for a string type VHDL object
                    X"DF"           -- legal, format specifier can be used
                    {X"DF"}         -- legal, format specifier can be used
                    'a'             -- legal
                    {"0XXX_1111"}   -- underscores are legal
                    "0001"          -- invalid, '"' need to be escaped
                    {"FALSE, FALSE, TRUE"}    -- invalid for a boolean type
                    '_'                       -- invalid
                    '0',                      -- comma after the literal is invalid
     

    Notice how none of the examples use 'b.

     

Reply

  • Did you try without the 'b part?

    In case you're not aware, the 6 letter error code can be used to display additional information:

    % nchelp ncsim SETNEL

    nchelp: 09.20-s031: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    ncsim/SETNEL =
            An attempt was made to force/nc_mirror a VHDL object using an invalid
            string or enumeration literal.
            Examples:
                    {"0001"}        -- legal
                    {"howdy"}       -- legal for a string type VHDL object
                    X"DF"           -- legal, format specifier can be used
                    {X"DF"}         -- legal, format specifier can be used
                    'a'             -- legal
                    {"0XXX_1111"}   -- underscores are legal
                    "0001"          -- invalid, '"' need to be escaped
                    {"FALSE, FALSE, TRUE"}    -- invalid for a boolean type
                    '_'                       -- invalid
                    '0',                      -- comma after the literal is invalid
     

    Notice how none of the examples use 'b.

     

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