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Double back-tick in parametrized macro in SV

sevent

Hello,

The following code does not compile in ncverilog v9.2, I think because of the double back-tick, yet it is an example directly out of the SystemVerilog 1800-2005 spec:

 `define msg(name) name``_suffix

module macro_test;

  initial
  begin
    $display(`msg(foo));
  end
endmodule

$ncverilog macro_test.v

ncverilog: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
file: macro_test.v
    $display(`msg(foo));
                     |
ncvlog: *E,EXPCPD (macro_test.v,7|21): expecting a valid compiler directive [16(IEEE)].
(`define macro: msg [macro_test.v line 1], file: macro_test.v line 7)
    $display(`msg(foo));
                     |
ncvlog: *E,NOTDIR (macro_test.v,7|21): `_suffix: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].

The `` is supposed to delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments.

Is this a bug with ncverilog?

Parents

  • Using -sv at this point is not an option due to legacy code causing syntax errors in other areas. Using the .sv extension on a more complete example still does not work:

     

    top.v:

    `define PREFIX foo
    `include "macro_test.sv"

    module top;

    endmodule

     

    macro_test.sv:

    `define MACRO(name) \
      force `PREFIX``name = 1'b1;

    module macro_test;

      reg fooA;

      initial
      begin
        `MACRO(A)
      end
    endmodule

     

    $ ncverilog top.v

    ncverilog: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
    file: top.v
        `MACRO(A)
                |
    ncvlog: *E,EXPCPD (macro_test.sv,10|12): expecting a valid compiler directive [16(IEEE)].
    (`define macro: MACRO [macro_test.sv line 1], `include file: macro_test.sv line 10, file: top.v line 2)
        `MACRO(A)
                |
    ncvlog: *E,NOTDIR (macro_test.sv,10|12): `A: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].

Reply

  • Using -sv at this point is not an option due to legacy code causing syntax errors in other areas. Using the .sv extension on a more complete example still does not work:

     

    top.v:

    `define PREFIX foo
    `include "macro_test.sv"

    module top;

    endmodule

     

    macro_test.sv:

    `define MACRO(name) \
      force `PREFIX``name = 1'b1;

    module macro_test;

      reg fooA;

      initial
      begin
        `MACRO(A)
      end
    endmodule

     

    $ ncverilog top.v

    ncverilog: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
    file: top.v
        `MACRO(A)
                |
    ncvlog: *E,EXPCPD (macro_test.sv,10|12): expecting a valid compiler directive [16(IEEE)].
    (`define macro: MACRO [macro_test.sv line 1], `include file: macro_test.sv line 10, file: top.v line 2)
        `MACRO(A)
                |
    ncvlog: *E,NOTDIR (macro_test.sv,10|12): `A: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].

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