Double back-tick in parametrized macro in SV

Hello,

The following code does not compile in ncverilog v9.2, I think because of the double back-tick, yet it is an example directly out of the SystemVerilog 1800-2005 spec:

 `define msg(name) name``_suffix

module macro_test;

  initial
  begin
    $display(`msg(foo));
  end
endmodule

$ncverilog macro_test.v

ncverilog: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
file: macro_test.v
    $display(`msg(foo));
                     |
ncvlog: *E,EXPCPD (macro_test.v,7|21): expecting a valid compiler directive [16(IEEE)].
(`define macro: msg [macro_test.v line 1], file: macro_test.v line 7)
    $display(`msg(foo));
                     |
ncvlog: *E,NOTDIR (macro_test.v,7|21): `_suffix: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].

The `` is supposed to delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments.

Is this a bug with ncverilog?