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VMM to Specman integration

sujntto

Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.

Urgent. If anybody knows any link pls share it.

Parents

  • There are many options for integrating e and SV together in the same testbench. Rather than trying to list them all here, I think it would be more productive if you contact your local Cadence AE who will gladly help you.

    If you have a UVM or OVM testbench it's easy, via TLM ports, to connect a complete mixed language environment.

    Anything else requires a more bespoke solution depending on your exact requirements, but there is a lot the tools can do to help.

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  • There are many options for integrating e and SV together in the same testbench. Rather than trying to list them all here, I think it would be more productive if you contact your local Cadence AE who will gladly help you.

    If you have a UVM or OVM testbench it's easy, via TLM ports, to connect a complete mixed language environment.

    Anything else requires a more bespoke solution depending on your exact requirements, but there is a lot the tools can do to help.

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