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VMM to Specman integration

sujntto

Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.

Urgent. If anybody knows any link pls share it.

  • There are many options for integrating e and SV together in the same testbench. Rather than trying to list them all here, I think it would be more productive if you contact your local Cadence AE who will gladly help you.

    If you have a UVM or OVM testbench it's easy, via TLM ports, to connect a complete mixed language environment.

    Anything else requires a more bespoke solution depending on your exact requirements, but there is a lot the tools can do to help.

  • Hi Stephen, Thanks for your reply.

    I can mention more information about what I am trying to do.

    In this project, we need to connect specman verification component(uVC) in VMM testbench.

    Basically we need to communicate between VMM channels and specman TLM ports.

    Please let us know if there is any feasibility to connect these two.
  •  There were two cases which were planned for connecting the VMM SV TB to the Specman eVC component

    1. Using Transcation based : -  Connecting the VMM channles to the Specman TLM ports (UVM)  (as described above)

    2. Using clock based  :-  Binding the SV TB (VMM) signals to the Specman eVC component using hdl_path() .

    Please let me know about  the feasible solution.

    Thanks

    Sujith

  • Hi Sujith.

    I see you're now connected to your local support guy, so we'll take the discussion offline.

    Perhaps once you're up and running though, you'd be kind enough to post a summary so other users can benefit from the experience?

    Regards, Steve

  • Steve, I am not getting any response from local support guy. Please let me know if you tried anything similar to this.

    I came to know that if the code is not following VMM, we can create a wrapper using SV UVM to expose TLM interfaces in the SV world, then  uvm_ml library can be used to connect e and SV. I have doubt here. Is it possible to create SV UVM wrapper on VMM TB ?

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