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VMM to Specman integration

sujntto

Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.

Urgent. If anybody knows any link pls share it.

Parents
  • Steve, I am not getting any response from local support guy. Please let me know if you tried anything similar to this.

    I came to know that if the code is not following VMM, we can create a wrapper using SV UVM to expose TLM interfaces in the SV world, then  uvm_ml library can be used to connect e and SV. I have doubt here. Is it possible to create SV UVM wrapper on VMM TB ?
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  • Steve, I am not getting any response from local support guy. Please let me know if you tried anything similar to this.

    I came to know that if the code is not following VMM, we can create a wrapper using SV UVM to expose TLM interfaces in the SV world, then  uvm_ml library can be used to connect e and SV. I have doubt here. Is it possible to create SV UVM wrapper on VMM TB ?
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