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VMM to Specman integration

sujntto

Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.

Urgent. If anybody knows any link pls share it.

Parents
  • Hi Stephen, Thanks for your reply.

    I can mention more information about what I am trying to do.

    In this project, we need to connect specman verification component(uVC) in VMM testbench.

    Basically we need to communicate between VMM channels and specman TLM ports.

    Please let us know if there is any feasibility to connect these two.
Reply
  • Hi Stephen, Thanks for your reply.

    I can mention more information about what I am trying to do.

    In this project, we need to connect specman verification component(uVC) in VMM testbench.

    Basically we need to communicate between VMM channels and specman TLM ports.

    Please let us know if there is any feasibility to connect these two.
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