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VMM to Specman integration

sujntto

Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.

Urgent. If anybody knows any link pls share it.

Parents
  •  There were two cases which were planned for connecting the VMM SV TB to the Specman eVC component

    1. Using Transcation based : -  Connecting the VMM channles to the Specman TLM ports (UVM)  (as described above)

    2. Using clock based  :-  Binding the SV TB (VMM) signals to the Specman eVC component using hdl_path() .

    Please let me know about  the feasible solution.

    Thanks

    Sujith
Reply
  •  There were two cases which were planned for connecting the VMM SV TB to the Specman eVC component

    1. Using Transcation based : -  Connecting the VMM channles to the Specman TLM ports (UVM)  (as described above)

    2. Using clock based  :-  Binding the SV TB (VMM) signals to the Specman eVC component using hdl_path() .

    Please let me know about  the feasible solution.

    Thanks

    Sujith
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