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Configurable IO pins in SystemVerilog

verifs

 Hi,

I am modelling a bfm for an IP using SystemVerilog. The model is completely class-based(OOPS) The "interface"  module has the pins of the BFM. I need one of the pins to be configurable as input or output, depending on the mode which is configured by the Host of the BFM.

I made it of type "wire" to declare it as "inout" in the "modport" of the "interface" file. But i can't use procedural assignment - this is the error i get -  "A net is not a legal lvalue in this context "

 Can anyone help me with this?

 

Thank you. 

Parents

  • How about something like:

    interface i (
      inout bd
    );
    reg is_output;
    reg bdreg;
    assign bd = (is_output)?bdreg:1'bz;
    endinterface

    You BFM must then control is_output to set the direction. You'd read the bd pin but would write the bdreg pin.

Reply

  • How about something like:

    interface i (
      inout bd
    );
    reg is_output;
    reg bdreg;
    assign bd = (is_output)?bdreg:1'bz;
    endinterface

    You BFM must then control is_output to set the direction. You'd read the bd pin but would write the bdreg pin.

Children
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