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Configurable IO pins in SystemVerilog

verifs

 Hi,

I am modelling a bfm for an IP using SystemVerilog. The model is completely class-based(OOPS) The "interface"  module has the pins of the BFM. I need one of the pins to be configurable as input or output, depending on the mode which is configured by the Host of the BFM.

I made it of type "wire" to declare it as "inout" in the "modport" of the "interface" file. But i can't use procedural assignment - this is the error i get -  "A net is not a legal lvalue in this context "

 Can anyone help me with this?

 

Thank you. 

Parents

  • Hi Stephen,

     Thank you so much for the quick reply :)

    Your solution looks great :) I think that's exactly what I needed :) I had implemented something similar in concept, but in the classes of my driver's but never thought or knew that I could have assign statements in the Interface module itself, that makes it so much easier and the code cleaner.

    I'll try it now and will let you know how it worked.

    Thanks again.

Reply

  • Hi Stephen,

     Thank you so much for the quick reply :)

    Your solution looks great :) I think that's exactly what I needed :) I had implemented something similar in concept, but in the classes of my driver's but never thought or knew that I could have assign statements in the Interface module itself, that makes it so much easier and the code cleaner.

    I'll try it now and will let you know how it worked.

    Thanks again.

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