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Assertions

livid

Hello

 

I am just embarking on our groups ABV strategy. We use VHDL for our IP development.

 

Currently, after a few iterations, we are going down the PSL assertion approach (as opposed to the System Verilog Assertion (SVA)) for embedding assertions at the sub-block level.

 

My understanding was that PSL is HDL language independant (ie PSL assertions can be used in Verilog/VHDL/System Verilog). However,the examples of SVA i have seen don't seem to be PSL assertions but System Verilog specific assertions. Therefore, the question is

               a) does System Verilog have its own set of assertions?

               b) If the answer to (a) is yes, how are the System Verilog and PSL assertions different?

 

Thanks

 

J.OSmany

 

  • Hi,

    a) yes, SVA and PSL are different

    b) I recommend the following document from the INCISIVE 10.2 release: Assertion Writing Guide Product Version 10.2 June 2011, Appendix A: PSL and SVA: Similarities and Differences

    Regards,

    Joerg.

  • Hi J.OSmany,


    We recently assisted a similar customer in India. They use VHDL for all their designs (mostly FPGA, some ASICs) and TBs in VHDL. They traditionally don't use heavy verification in pre-silicon but are getting to it largely due to extended debug time on the FPGA. Here is what we arrived at:

    1. Use PSL/VHDL-08 for assertions & functional coverage (cover property).
    2. Use advanced VHDL-08 techniques for extended testbnech techniques & modeling

    The choice bet'n SV & VHDL finally came down to - why learn a new language when new VHDL (2008 version) can support many of what they needed. One thing that VHDL-08 doesn't have yet is constrained random generation but Jim Lewis has a package for it, if interested.

    Another factor was the commercial/business angle - VHDL simulator (with 2008 support) is enough than adding mixed language features/licenses.

    HTH
    Srini
    http://www.cvcblr.com

    Here is detailed agenda of what we covered during their team ramp-up:

  • Introduction to VHDL-2008
  • Modeling Enhancements
  • Multi-line Comments
  • Sequential Statements
  • Concurrent Statements
  • New (IF, Case generate Statement)
  • Unconstrained arrays, records
  • Operators Changes
  • Expansion of existing operators
  • New operations
  • IP Encryption
  • Verification specific features:
  • TEXTIO enhancements
  • Extern signals
  • Force release
  • ENV package
  • New Context declarations
  • Generic enhancements
  • The whole of PSL

    •  

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