Assertions

Hello

I am just embarking on our groups ABV strategy. We use VHDL for our IP development.

Currently, after a few iterations, we are going down the PSL assertion approach (as opposed to the System Verilog Assertion (SVA)) for embedding assertions at the sub-block level.

My understanding was that PSL is HDL language independant (ie PSL assertions can be used in Verilog/VHDL/System Verilog). However,the examples of SVA i have seen don't seem to be PSL assertions but System Verilog specific assertions. Therefore, the question is

               a) does System Verilog have its own set of assertions?

               b) If the answer to (a) is yes, how are the System Verilog and PSL assertions different?

Thanks

J.OSmany