Stats

  • Locked Locked
  • Replies 1
  • Subscribers 65
  • Views 1878
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Failed to find SETUP/HOLD timingcheck

tswong

I am performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?

Thanks!

Parents

  • Hello,

    The message is indicating that you have HOLD and SETUP timing checks in the sdf file, but there is no SETUP or HOLD timing checks specified in the verilog specify block of the RTL.  Consequently the simulator is not able to annotate those timing checks.  This will not cause the simulator to exit or fail, but it will result in the timing checks in the sdf not being performed.

    By the way, If at all possible I would recommend using ncverilog rather than verilog-xl (VXL).  To do that simply replace the "verilog" on the command line with "ncverilog".  That is more than likely not going to fix the problem, but going forward I would suggest using nc-verilog because it is the simulator that is continually being updated with newer functionality.

    Best regards,
    Mickey
Reply

  • Hello,

    The message is indicating that you have HOLD and SETUP timing checks in the sdf file, but there is no SETUP or HOLD timing checks specified in the verilog specify block of the RTL.  Consequently the simulator is not able to annotate those timing checks.  This will not cause the simulator to exit or fail, but it will result in the timing checks in the sdf not being performed.

    By the way, If at all possible I would recommend using ncverilog rather than verilog-xl (VXL).  To do that simply replace the "verilog" on the command line with "ncverilog".  That is more than likely not going to fix the problem, but going forward I would suggest using nc-verilog because it is the simulator that is continually being updated with newer functionality.

    Best regards,
    Mickey
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.