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NC-verilog logical bug

Aiya

 I found a logical bug of simulation RTL code using NC-verilog.

Here is the test RTL code of mux implementation,

the input data of mux options are all zeroes (1'b0) 

the select signal is unknown (2'bxx)

The output result of do0 = 1'bx, do1 = 1'bx,  do2 = 1'b0,

varies depending on the coding style,

 Is this a bug of NC-verilog tool ? Can it be fixed ?

module  muxa(
input   wire  [ 1:0]  sel   ,
input   wire          di0   ,
input   wire          di1   ,
input   wire          di2   ,
input   wire          di3   ,
output  reg           do0   ,
output  wire          do1   ,
output  wire          do2  
);

always@*
  case(sel)
    2'h0: do0 = di0;
    2'h1: do0 = di1;
    2'h2: do0 = di2;
    2'h3: do0 = di3;
  endcase

wire  [3:0] di    = {di3, di2, di1, di0};
assign      do1   = di[sel];
assign      do2   = sel[1] ? (sel[0] ? di3 : di2) : (sel[0] ? di1 : di0);

endmodule

  • This is not a bug.

    This is the correct behavior as defined by the language standard.

    Regards,

    Shalom

  • Thank you Shalom, but could you explain in more detail ?

     Logically, the output of mux should 1'b0 right?

    But using case or index coding style for mux implementation is more readable and explicit

    Is the do2 is the only option if I want to get correct logic output ? Or any syntax can be added to solve this ?

  • I think the mistake you're making is that you are expecting the tool to do logic synthesis and give you the output of pure boolean operations.
    A Verilog simulator is actually just an interpreter for your code, it executes program statements sequentially, following rules of the language.
    The simulator does not know that you're modelling a mux.

    In your case statement you don't have a default case, so if "sel" is 2'bxx, none of your explicit branches match, and do0 is not assigned.
    Remember 'bx in Verilog doesn't necessarily mean "don't care", it is just a symbol, so 2'bxx won't match 2'b00, 2'b01, 2'b10 or 2'b11.

    Your do2 is modelled differently and works, because it's basically a set of nested "if" statements.
    if (sel[0]=1) will fail when sel=2'bxx, so you drop into the else branch. But the do0 case doesn't have an "else", i.e. default branch to drop into.

  • Thanks a lot StephenH. You answered in great detail.

    so I just add a default option to the case statement 

    then my nc-verilog simulation and logic synthsis are matched right?

    always@*
      case(sel)
        2'h0  : do0 = di0;
        2'h1  : do0 = di1;
        2'h2  : do0 = di2;
        2'h3  : do0 = di3;
      default : do0 = di0;
      endcase

    Thank you again ^^

  • Aiya said:

    then my nc-verilog simulation and logic synthsis are matched right?

    Not quite! Your synthesis *may* do that, but it may not, depending on the logic tree it builds or the cells it uses. You could take a pessimistic approach and assign do0 = 2'bxx if sel is not one of your explicit values, and this is more likely to match netlist simulations where x propagation tends to be the way to spot failures. However you might make your model do something more like "realistic", e.g. if all inputs are identical, sel doesn't matter. This may still not exactly match your synthesis but might be a more useful model to avoid x explosion. default: do0 = (di0 == di1 == di2 == di3) ? di0 : 'bx; Note the above test expression is pseudo code for ease of typing! :)

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