NC-verilog logical bug

 I found a logical bug of simulation RTL code using NC-verilog.

Here is the test RTL code of mux implementation,

the input data of mux options are all zeroes (1'b0) 

the select signal is unknown (2'bxx)

The output result of do0 = 1'bx, do1 = 1'bx,  do2 = 1'b0,

varies depending on the coding style,

 Is this a bug of NC-verilog tool ? Can it be fixed ?

module  muxa(
input   wire  [ 1:0]  sel   ,
input   wire          di0   ,
input   wire          di1   ,
input   wire          di2   ,
input   wire          di3   ,
output  reg           do0   ,
output  wire          do1   ,
output  wire          do2  
);

always@*
  case(sel)
    2'h0: do0 = di0;
    2'h1: do0 = di1;
    2'h2: do0 = di2;
    2'h3: do0 = di3;
  endcase

wire  [3:0] di    = {di3, di2, di1, di0};
assign      do1   = di[sel];
assign      do2   = sel[1] ? (sel[0] ? di3 : di2) : (sel[0] ? di1 : di0);

endmodule