• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. NC VHDL "simulation error"

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 1116
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

NC VHDL "simulation error"

kovibb
kovibb over 13 years ago
Hi everybody, I use Design Entry HDL for scheme and layout design a few years. Now i want to upgrade me with VHDL simulation so i try to use NC VHDL simulator for that. I start with basis and don't run a lot of time I hit to first problem. When i set up simulator, generate netlist from schematic and generate testbanch than i try it simulate. Simulator show mi this error message after binding and before compilating design process: img256.imageshack.us/.../diffncvhdl.png Just to be sure, I attach link for project: rapidshare.com/.../dff.zip Schematic contains a one simply D flip-flop device. Code is write in VDHL language. Can you give me please same advices or solutions? Thank all
  • Cancel
Parents
  • StephenH
    StephenH over 13 years ago
    From your screenshot it looks like you are trying to run ncvhdl under Windows from Allegro 16.0, right? That version isn't supported any more, as it's 5 years old! Cadence doesn't support Windows for the Incisive simulator (which ncvhdl is part of), it's been about 6 years since we dropped support for Windows. If you have access to a Solaris or Linux machine, then you should be able to install Allegro (SPB) on on of these platforms, where we do fully support the logic simulator. The latest SPB version is 16.5 and is available from http://downloads.cadence.com/. Regards, Steve.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • StephenH
    StephenH over 13 years ago
    From your screenshot it looks like you are trying to run ncvhdl under Windows from Allegro 16.0, right? That version isn't supported any more, as it's 5 years old! Cadence doesn't support Windows for the Incisive simulator (which ncvhdl is part of), it's been about 6 years since we dropped support for Windows. If you have access to a Solaris or Linux machine, then you should be able to install Allegro (SPB) on on of these platforms, where we do fully support the logic simulator. The latest SPB version is 16.5 and is available from http://downloads.cadence.com/. Regards, Steve.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information