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use generated clock to sample the logic value driven by main clock.

HI, all
Now I encountered one problem when I do RTL simulation. there is one main clock named 'main_clk" in the design, and another clock named 'clk_div2' which is generated from 'main_clk', it is divided by two, I want to use 'clk_div2' to sample the logic signal driven by 'main_clk', but I found I can not get the correct value, it seems that 'clk_div2' sampled the next cycle value, not the current one. what causes that ? but after synthesizing and building clock tree, the problem disappeared, why?

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TAM1 over 13 years ago

Do you have access to information on support.cadence.com? If so, there is an App-Note that explains why you should use a blocking vs. a non-blocking assignment in your clock tree. There are some other race condition issues that you can look for too.
Race Conditions
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TAM1 over 13 years ago

Do you have access to information on support.cadence.com? If so, there is an App-Note that explains why you should use a blocking vs. a non-blocking assignment in your clock tree. There are some other race condition issues that you can look for too.
Race Conditions
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