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$nc_mirror issues not seen within this forum

Hi,

I am using the $nc_mirror system task to mirror a VHDL signal to a system verilog environment. The strange thing is that if i include the "verbose" option then it works fine except that there are lots of messages written to screen.

If i remove the "verbose" option then i get an ncsim.err exception.

Works: $nc_mirror("destination","source","verbose");

Doesnt work: $nc_mirror("destination","source");

Doesnt work: $nc_mirror("destination","source","");

Is there a string that can replace verbose which will minimize the amount of messages written to screen?

Any help would be greatly appreciated.

Thanks

Parents

damo1865 over 13 years ago

Hi Tam1,
Thanks for the quick response. I have copied the internal failure below. Im just surprised that there is no keyword which is the opposite of verbose to switch off error messaging.
Regards,damo1865
csi-ncsim - CSI: Command line:
ncsim
-f /var/vob/timm/module/vob/units/bccu/simulation/damien/INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101/ncsim.args
-INPUT @source /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/files/tcl/uvm_sim.tcl
+UVM_VERBOSITY=UVM_LOW
+define+OP_CHECK_ON
-sv_lib /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/lib/libuvmpli.so
-gui
+UVM_TESTNAME=coarse_rand_te0
-COVTEST te0r
-COVOVERWRITE
-TCL
-MESSAGES
-SV_LIB /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/lib/libuvmdpi.so
+EMGRLOG ./logs/coarse_rnd_0.log
-XLSTIME 1332423364
-XLKEEP
-XLMODE ./INCA_libs/irun.lnx86.10.20.nc
-RUNMODE
-CDSLIB ./INCA_libs/irun.lnx86.10.20.nc/cds.lib
-HDLVAR ./INCA_libs/irun.lnx86.10.20.nc/hdl.var
-XLNAME irun
-XLVERSION TOOL: irun 10.20-s100
-XLNAME ./INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101
-CHECK_VERSION TOOL: irun 10.20-s100
-LOG_FD 4
-LOG_FD_NAME ./logs/coarse_rnd_0.log
-cmdnopsim
-runscratch /var/vob/timm/module/vob/units/bccu/simulation/damien/INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101
csi-ncsim - CSI: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 200008 NS + 1
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim 10.20-s100
HOSTNAME: vihlc697
OPERATING SYSTEM: Linux 2.6.18-274.3.1.el5 #1 SMP Fri Aug 26 18:49:02 EDT 2011 x86_64
MESSAGE: sv_seghandler - trapno -1 addr(0x00000004)
-----------------------------------------------------------------
csi-ncsim - CSI: Cadence Support Investigation, recording details
Simulator Snap Shot: wma (SSS_WMA) in snapshot worklib.top:sv (SSS)
Intermediate File: root (IF_ROOT) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: register declaration (VST_D_REG) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 15, position 21
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bit rtl_chint
Source : bit [11:0] rtl_chint;
Position: ^
Verilog Syntax Tree: bit type (VST_T_BIT) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
Decompile: bit
Simulator Snap Shot: fta (SSS_FTA) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: indexed vector type (VST_T_INDEXED_VEC) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bit
Verilog Syntax Tree: overlay table (VST_OVERLAY_TABLE) in verilog_package worklib.uvm_pkg:sv (SIG) <0x0fb43995>
Decompile: bccu_xactor_pkg::bccu_channel
Intermediate File: ffstructa (IF_FFSTRUCTA) in snapshot worklib.top:sv (SSS)
Intermediate File: data block (IF_BLK) in snapshot worklib.top:sv (SSS)
Simulator Snap Shot: mirrors (SSS_MIRRORS) in snapshot worklib.top:sv (SSS)
Intermediate File: array of pointers (IF_PTRBLK) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: class declaration (VST_D_CLASS) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 9, position 17
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bccu_xactor_pkg::bccu_channel
Source : class bccu_channel extends uvm_subscriber #(bccu_data);
Position: ^
Verilog Syntax Tree: task declaration (VST_D_TASK) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 502, position 27
Scope: bccu_xactor_pkg::bccu_channel::get_chint
Decompile: get_chint
Source : task bccu_channel::get_chint();
Position: ^
Native Code Stream (t=200008000000): Task get_chint (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 502 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 518, position 14
Scope: worklib.bccu_xactor_pkg::bccu_channel@11237_6.get_chint
Source : 2: $nc_mirror("rtl_chint","top.DUT_wrapper.bccu_i:all_chint[2]");
Position: ^
Native Code Stream (t=200008000000): Task linear_walk (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 227 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 231, position 10
Scope: worklib.bccu_xactor_pkg::bccu_channel@11237_6.linear_walk
Source : get_chint();
Position: ^
Native Code Stream (t=200008000000): Task run (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 169 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 200, position 18
Scope: worklib.bccu_xactor_pkg::bccu_channel@3958_3.run
Source : linear_walk();
Position: ^
Native Code Stream (t=200008000000): Task run_phase (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_component.svh, line: 2301 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_component.svh, line 2302, position 4
Scope: worklib.uvm_pkg::uvm_component@3958_3.run_phase
Source : run();
Position: ^
Native Code Stream (t=200008000000): Task exec_task (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_common_phases.svh, line: 255 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_common_phases.svh, line 258, position 22
Scope: worklib.uvm_pkg::uvm_run_phase::exec_task
Source : comp_.run_phase(phase);
Position: ^
Native Code Stream (t=200008000000): Scope unmblk1 (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line: 137 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line 145, position 16
Scope: worklib.uvm_pkg::uvm_task_phase::execute.unmblk1
Source : exec_task(comp,phase);
Position: ^
Native Code Stream (t=200008000000): Parallel block sub-process (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line/pos: 137/10 in worklib.uvm_pkg [package])
Verilog Syntax Tree: sequential block statement (VST_S_SEQ_BLOCK) in verilog_package worklib.uvm_pkg:sv (VST)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line 137, position 10
Scope: uvm_pkg::uvm_task_phase::execute.unmblk1
Source : begin
Position: ^
csi-ncsim - CSI: investigation complete took 0.046 secs, send this file to Cadence Support
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Reply

damo1865 over 13 years ago

Hi Tam1,
Thanks for the quick response. I have copied the internal failure below. Im just surprised that there is no keyword which is the opposite of verbose to switch off error messaging.
Regards,damo1865
csi-ncsim - CSI: Command line:
ncsim
-f /var/vob/timm/module/vob/units/bccu/simulation/damien/INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101/ncsim.args
-INPUT @source /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/files/tcl/uvm_sim.tcl
+UVM_VERBOSITY=UVM_LOW
+define+OP_CHECK_ON
-sv_lib /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/lib/libuvmpli.so
-gui
+UVM_TESTNAME=coarse_rand_te0
-COVTEST te0r
-COVOVERWRITE
-TCL
-MESSAGES
-SV_LIB /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/lib/libuvmdpi.so
+EMGRLOG ./logs/coarse_rnd_0.log
-XLSTIME 1332423364
-XLKEEP
-XLMODE ./INCA_libs/irun.lnx86.10.20.nc
-RUNMODE
-CDSLIB ./INCA_libs/irun.lnx86.10.20.nc/cds.lib
-HDLVAR ./INCA_libs/irun.lnx86.10.20.nc/hdl.var
-XLNAME irun
-XLVERSION TOOL: irun 10.20-s100
-XLNAME ./INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101
-CHECK_VERSION TOOL: irun 10.20-s100
-LOG_FD 4
-LOG_FD_NAME ./logs/coarse_rnd_0.log
-cmdnopsim
-runscratch /var/vob/timm/module/vob/units/bccu/simulation/damien/INCA_libs/irun.lnx86.10.20.nc/vihlc697_12101
csi-ncsim - CSI: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 200008 NS + 1
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim 10.20-s100
HOSTNAME: vihlc697
OPERATING SYSTEM: Linux 2.6.18-274.3.1.el5 #1 SMP Fri Aug 26 18:49:02 EDT 2011 x86_64
MESSAGE: sv_seghandler - trapno -1 addr(0x00000004)
-----------------------------------------------------------------
csi-ncsim - CSI: Cadence Support Investigation, recording details
Simulator Snap Shot: wma (SSS_WMA) in snapshot worklib.top:sv (SSS)
Intermediate File: root (IF_ROOT) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: register declaration (VST_D_REG) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 15, position 21
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bit rtl_chint
Source : bit [11:0] rtl_chint;
Position: ^
Verilog Syntax Tree: bit type (VST_T_BIT) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
Decompile: bit
Simulator Snap Shot: fta (SSS_FTA) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: indexed vector type (VST_T_INDEXED_VEC) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bit
Verilog Syntax Tree: overlay table (VST_OVERLAY_TABLE) in verilog_package worklib.uvm_pkg:sv (SIG) <0x0fb43995>
Decompile: bccu_xactor_pkg::bccu_channel
Intermediate File: ffstructa (IF_FFSTRUCTA) in snapshot worklib.top:sv (SSS)
Intermediate File: data block (IF_BLK) in snapshot worklib.top:sv (SSS)
Simulator Snap Shot: mirrors (SSS_MIRRORS) in snapshot worklib.top:sv (SSS)
Intermediate File: array of pointers (IF_PTRBLK) in snapshot worklib.top:sv (SSS)
Verilog Syntax Tree: class declaration (VST_D_CLASS) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 9, position 17
Scope: bccu_xactor_pkg::bccu_channel
Decompile: bccu_xactor_pkg::bccu_channel
Source : class bccu_channel extends uvm_subscriber #(bccu_data);
Position: ^
Verilog Syntax Tree: task declaration (VST_D_TASK) in verilog_package worklib.bccu_xactor_pkg:sv (VST)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 502, position 27
Scope: bccu_xactor_pkg::bccu_channel::get_chint
Decompile: get_chint
Source : task bccu_channel::get_chint();
Position: ^
Native Code Stream (t=200008000000): Task get_chint (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 502 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 518, position 14
Scope: worklib.bccu_xactor_pkg::bccu_channel@11237_6.get_chint
Source : 2: $nc_mirror("rtl_chint","top.DUT_wrapper.bccu_i:all_chint[2]");
Position: ^
Native Code Stream (t=200008000000): Task linear_walk (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 227 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 231, position 10
Scope: worklib.bccu_xactor_pkg::bccu_channel@11237_6.linear_walk
Source : get_chint();
Position: ^
Native Code Stream (t=200008000000): Task run (file: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line: 169 in worklib.bccu_xactor_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /var/vob/timm/module/vob/units/bccu/source/sv/tb/bccu_tb/bccu_model/bccu_channel.sv, line 200, position 18
Scope: worklib.bccu_xactor_pkg::bccu_channel@3958_3.run
Source : linear_walk();
Position: ^
Native Code Stream (t=200008000000): Task run_phase (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_component.svh, line: 2301 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_component.svh, line 2302, position 4
Scope: worklib.uvm_pkg::uvm_component@3958_3.run_phase
Source : run();
Position: ^
Native Code Stream (t=200008000000): Task exec_task (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_common_phases.svh, line: 255 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_common_phases.svh, line 258, position 22
Scope: worklib.uvm_pkg::uvm_run_phase::exec_task
Source : comp_.run_phase(phase);
Position: ^
Native Code Stream (t=200008000000): Scope unmblk1 (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line: 137 in worklib.uvm_pkg [package])
Verilog Syntax Tree: task declaration (VST_D_TASK) in snapshot worklib.top:sv (SSS)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line 145, position 16
Scope: worklib.uvm_pkg::uvm_task_phase::execute.unmblk1
Source : exec_task(comp,phase);
Position: ^
Native Code Stream (t=200008000000): Parallel block sub-process (file: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line/pos: 137/10 in worklib.uvm_pkg [package])
Verilog Syntax Tree: sequential block statement (VST_S_SEQ_BLOCK) in verilog_package worklib.uvm_pkg:sv (VST)
File: /opt/INCISIV_10.20.030/CEN/tools/uvm/uvm_lib/uvm_sv/sv/base/uvm_task_phase.svh, line 137, position 10
Scope: uvm_pkg::uvm_task_phase::execute.unmblk1
Source : begin
Position: ^
csi-ncsim - CSI: investigation complete took 0.046 secs, send this file to Cadence Support
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