Stats

Locked Locked
Replies 4
Subscribers 66
Views 14834
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Declaring array of uniquely parameterized classes

In my SystemVerilog environment, I have an array of a class typefor which I need to customize instantiation parameters for each class in the array. With all classes the same, I can do

my_class #(.PARAM1(32), .PARAM2(8)) classes[8];

However, I can't figure out how to customize the PARAM1 and PARAM2 parameters for each specialization. Is this possible?

Parents

benbuchanan over 13 years ago

Thanks, and I agree.
Cancel
Vote Up 0 Vote Down

Cancel

Reply

benbuchanan over 13 years ago

Thanks, and I agree.
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.