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SystemVerilog modport question

SCollins

Hi All,

I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the MSB of the bus.

I believe the easiest way of doing this is to use modports - a master modport and a different modport for each slave. The interface code would then look something like this (modports are on single lines for compactness):

interface data_bus_if

logic [1:0] data;

modport master (output data);

modport slave0 (input .data_bit(data[0]));

modport slave1 (input .data_bit(data[1]));

endinterface : data_bus_if

I'd imagine this scenario is quite common but Incisive doesn't appear to support modport expressions. How can I implement the interface so that it compiles with Incisive?

Many thanks!

  • Hi Sean (?)

    Although Cadence has occasionally had requests to support that style of modport expression, it's not been of of the more popular features and as such hasn't been implemented yet. If you care to file a support request for the same, we can get you added to the list of people officially requesting it, which can help us when planning which features to implement next.

    The following adaptation of your code does work in Incisive. Eventually you'd be able to replace the separate sub-interfaces with modports, as per the examples in the LRM.

     

    interface slave_if ( input data_bit );

    endinterface

    interface data_bus_if;

    logic [1:0] data;

    modport master (output data);

    slave_if slave0 (.data_bit(data[0]));

    slave_if slave1 (.data_bit(data[1]));

    endinterface : data_bus_if

     
    Even if we did support the exact syntax that you're requesting, it still has the limitation that you would have to declare a new modport for each slave, which would be a nuisance if the number were variable. You can make this more generic by using a generate block:
     
    interface slave_if ( input data_bit );
    endinterface

    interface data_bus_if;
    parameter NUM_SLAVES = 2;
    logic [NUM_SLAVES-1:0] data;

    modport master (output data);

    generate 
    for(genvar i = 0; i < NUM_SLAVES; i++) begin : slave_gen
      slave_if slave (.data_bit(data[i]));
    end
    endgenerate

    endinterface : data_bus_if
     
     
    Hope this helps! 

     

  • Hi Steve,

    Thanks for responding, your workaround seems a good solution, however, I'm having problems elaborating my example design when I use a generate statement to create the slave sub-interface instances.

    My code for a slave is:

    module slave (slave_sub_if port);

    <slave code>

    endmodule 

    In my top level where I instantiate each slave, I've used the following code:

    slave slave_inst0 (.port data_bus_if_inst.slave_gen[0].slave_sub_if_inst);

    Incisive reports the following error during elaboration (highlighting the slave_sub_if_inst name):

    ncelab: *E,CUIOAI (...etc): Illegal interface port connection through a generate or array instance

    The block within my generate statement is named "slave_gen", which is the same as the block in your code.

    How should I specify the name of my sub-interface instance to ensure that my design elaborates?

    BTW, I should mention that my design elaborated when I simply instantiated 2 instances of my slave (without a generate statement).

    Thanks!

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