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SystemVerilog modport question

SCollins

Hi All,

I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the MSB of the bus.

I believe the easiest way of doing this is to use modports - a master modport and a different modport for each slave. The interface code would then look something like this (modports are on single lines for compactness):

interface data_bus_if

logic [1:0] data;

modport master (output data);

modport slave0 (input .data_bit(data[0]));

modport slave1 (input .data_bit(data[1]));

endinterface : data_bus_if

I'd imagine this scenario is quite common but Incisive doesn't appear to support modport expressions. How can I implement the interface so that it compiles with Incisive?

Many thanks!

Parents

  • Hi Steve,

    Thanks for responding, your workaround seems a good solution, however, I'm having problems elaborating my example design when I use a generate statement to create the slave sub-interface instances.

    My code for a slave is:

    module slave (slave_sub_if port);

    <slave code>

    endmodule 

    In my top level where I instantiate each slave, I've used the following code:

    slave slave_inst0 (.port data_bus_if_inst.slave_gen[0].slave_sub_if_inst);

    Incisive reports the following error during elaboration (highlighting the slave_sub_if_inst name):

    ncelab: *E,CUIOAI (...etc): Illegal interface port connection through a generate or array instance

    The block within my generate statement is named "slave_gen", which is the same as the block in your code.

    How should I specify the name of my sub-interface instance to ensure that my design elaborates?

    BTW, I should mention that my design elaborated when I simply instantiated 2 instances of my slave (without a generate statement).

    Thanks!

Reply

  • Hi Steve,

    Thanks for responding, your workaround seems a good solution, however, I'm having problems elaborating my example design when I use a generate statement to create the slave sub-interface instances.

    My code for a slave is:

    module slave (slave_sub_if port);

    <slave code>

    endmodule 

    In my top level where I instantiate each slave, I've used the following code:

    slave slave_inst0 (.port data_bus_if_inst.slave_gen[0].slave_sub_if_inst);

    Incisive reports the following error during elaboration (highlighting the slave_sub_if_inst name):

    ncelab: *E,CUIOAI (...etc): Illegal interface port connection through a generate or array instance

    The block within my generate statement is named "slave_gen", which is the same as the block in your code.

    How should I specify the name of my sub-interface instance to ensure that my design elaborates?

    BTW, I should mention that my design elaborated when I simply instantiated 2 instances of my slave (without a generate statement).

    Thanks!

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