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  3. How to probe VHDL function variables in ncsim?

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How to probe VHDL function variables in ncsim?

venkub
venkub over 12 years ago

Hi,

 I need to view the variables used inside a function in simvision waveform viewer.

 How to add a probe to view these variables in the viewer?

Thanks,
Venkat 

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  • David Rogoff
    David Rogoff over 10 years ago
    Anyone? I also have this issue and a similar one: variables inside procedures can be selected in SimVision but can't be probed so it shows nothing. As a temporary work-around, I change these to shared variables in the parent architecture. It seems like SimVision treats VHDL procedures and functions like it does automatic tasks in SystemVerilog and won't display any internal variables.
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  • Mickey
    Mickey over 10 years ago

    To probe VHDL variables you need to include -variable in the probe tcl command, eg.

    database -open waves.shm -default -shm

    probe tb.top -all -depth all -variables

    The above command would probe all ports and internal signals at the top.top scope and below and will also include any vhdl variables.

    Hope that helps.

    Best regards,
    Mickey

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  • David Rogoff
    David Rogoff over 10 years ago
    Thanks for replying but that doesn't seem to be the issue. I am showing variables but I get errors when trying to probe variables that are inside a procedure. Again, I think it's because simvision can't deal with non-static objects. It only shows things that exist after elaboration.
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