• Home
  • :
  • Community
  • :
  • Forums
  • :
  • Functional Verification
  • :
  • files required to use vams netlist

Functional Verification Forums

files required to use vams netlist

Visbi
Visbi over 4 years ago

Hi All,

I am new to mixed singal verifcation. I want to run mixed signal verifcation using irun. I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence schematic. Then I created the netlist.vams of whole design using ADE-L (AMS simulator).

Since digital team is using ncsim to verify funcationality, I would like to use the same environment and test benches by just replacing entire verilog modules to single netlist.vams file.

Can anybody provide me step by step help for this?

-Thanks in advance.

  • Reply
  • Cancel
  • Cancel
  • shalem7
    shalem7 over 4 years ago

    Hi, 

    Visbi said:
    I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence schematic

     I hope you included disciplines.vams file in your verilog-A module.

    To run the simulation We need,

    -> analog control file which specifies the type of analysis,time,simulator options etc.

        Ex: tran tran stop=3.5m

      We can pass this file through command line.

      irun *.vams -analogcontrol sim_control.scs

     I hope this helps.

    Thanks,

    Shalem

    • Cancel
    • Up 0 Down
    • Reply
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.