I am new to mixed singal verifcation. I want to run mixed signal verifcation using irun. I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence schematic. Then I created the netlist.vams of whole design using ADE-L (AMS simulator).
Since digital team is using ncsim to verify funcationality, I would like to use the same environment and test benches by just replacing entire verilog modules to single netlist.vams file.Can anybody provide me step by step help for this?-Thanks in advance.
Visbi said:I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence schematic
I hope you included disciplines.vams file in your verilog-A module.
To run the simulation We need,
-> analog control file which specifies the type of analysis,time,simulator options etc.
Ex: tran tran stop=3.5m
We can pass this file through command line.
irun *.vams -analogcontrol sim_control.scs
I hope this helps.