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please help on verilog and vhdl combination problems

victorhan

Hi Candence,

I met a problem in using verilog and vhdl:

1) I use verilog to make a testbench while the DUT all are made by VHDL

2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.

So would you like to give me some suggestions on how to initial memories in VHDL designs through  verilog testbench?

Thanks!

Parents

  • Thanks for your kindly reply. It works by using $nc_force.

    BTW, how can I transfer a integer variable from verilog to VHDL?

    As the code shows bellow:

    tb_top is verilog module;

    vhdl_top and bellows are vhdl module.

    module tb_top;

    integer i;

    $nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);

    endmodule

    The ERROR message is:

    expecting a integer index i.

     

Reply

  • Thanks for your kindly reply. It works by using $nc_force.

    BTW, how can I transfer a integer variable from verilog to VHDL?

    As the code shows bellow:

    tb_top is verilog module;

    vhdl_top and bellows are vhdl module.

    module tb_top;

    integer i;

    $nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);

    endmodule

    The ERROR message is:

    expecting a integer index i.

     

Children
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