please help on verilog and vhdl combination problems

Hi,

I think we can only do this sort of initializing [vhdl DUT,verilog testbench and vice-versa]by using $nc_force and $nc_release.You can try this.

 Please correct me if I am wrong.

 Regards,

Shalem

Thanks for your kindly reply. It works by using $nc_force.

BTW, how can I transfer a integer variable from verilog to VHDL?

As the code shows bellow:

tb_top is verilog module;

vhdl_top and bellows are vhdl module.

module tb_top;

integer i;

$nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);

endmodule

The ERROR message is:

expecting a integer index i.

I am not sure about the error.I did not inderstand the # in #data[i].

data[i] also needs to be in  " ".

nc_force command has to be like this.

If your memarray is of size 5,each single bit

$nc_force("tb_top.vhdl_top:ocmem:memarry" , "10010"); //if it is a single bit. 

Regards,

Shalem

The important thing is not about how to use #data[i].

It's how transfer a integer i from the top file in verilog to the inner module writen by VHDL.

As the code shows bellow:

At test bench top file which was written in verilog:

integer i;

for (i=0, i < 4096, i=i+1) begin

$nv_force("tb_top.arcsys:ocram:aram:now:mem_int[i]","#data[i]","verbose");

end

The array mem_int is beneth vhdl designed module, so my question is how can I transfer

the integer i to VHDL designed module mem_int?

 I believe the problem is that you are passing the index into the $nc_force command as a variable rather than a constant. The task is expecting a string with the name of a signal. It isn't going to parse that name and do variable substitution in it. You need to do that yourself.

Try something like this:

integer i;
reg [72*8:1] targetname, srcname;

initial
for (i=0, i < 4096, i=i+1) begin
  $swrite(targetname,"tb_top.arcsys:ocram:aram:now:mem_int[%0d]",i); 
  $swrite(srcname,"#data[%0d]",i);  // I'm not sure exactly what #data refers to, but we're not talking about that...
  $nv_force(targetname,srcname,"verbose");
end

 Hi TAM,

Thanks for your kindly reply.

I have tried the method that you told me.

But it's still useless, the variable i still can't be transfered from verilog top file to the deep VHDL.

Thanks,

Shaonan

 I put together a small example and this code appears to work:

   reg [7:0] data [31:0];
   integer i;
   reg [72:1] destname;
   reg [7:0] dataval;

    for ( i=0; i < 32; i=i+1 ) data[i] = i;

    for ( i=0; i < 32; i=i+1 )
    begin
      $swrite(destname,"s1:mem(%0d)",i);
      dataval = data[i];
      $nc_deposit(destname,"#dataval");
    end

You may want to use $nc_deposit rather than $nc_force if you want to later be able to write to the memory later from inside the VHDL model.