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please help on verilog and vhdl combination problems

victorhan

Hi Candence,

I met a problem in using verilog and vhdl:

1) I use verilog to make a testbench while the DUT all are made by VHDL

2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.

So would you like to give me some suggestions on how to initial memories in VHDL designs through  verilog testbench?

Thanks!

Parents

  •  I put together a small example and this code appears to work:

     

       reg [7:0] data [31:0];
       integer i;
       reg [72:1] destname;
       reg [7:0] dataval;

        for ( i=0; i < 32; i=i+1 ) data[i] = i;

        for ( i=0; i < 32; i=i+1 )
        begin
          $swrite(destname,"s1:mem(%0d)",i);
          dataval = data[i];
          $nc_deposit(destname,"#dataval");
        end

    You may want to use $nc_deposit rather than $nc_force if you want to later be able to write to the memory later from inside the VHDL model.

Reply

  •  I put together a small example and this code appears to work:

     

       reg [7:0] data [31:0];
       integer i;
       reg [72:1] destname;
       reg [7:0] dataval;

        for ( i=0; i < 32; i=i+1 ) data[i] = i;

        for ( i=0; i < 32; i=i+1 )
        begin
          $swrite(destname,"s1:mem(%0d)",i);
          dataval = data[i];
          $nc_deposit(destname,"#dataval");
        end

    You may want to use $nc_deposit rather than $nc_force if you want to later be able to write to the memory later from inside the VHDL model.

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